External Bus on 440GP

Sibi · External Since: Sep 24, 2005 Posts: 2

Hello all,

I have a question about linux on 440gp and a custom board.

We use the Universal boot-loader, U-boot, to initialize the board and
then, boot linux. The flash chip on the board is 4 MB in size.

I'm trying to access the flash chip (attached to the External Bus
Interface) in a custom device driver running in linux. The behavior
I'm seeing is this: when the EBC0_B0CR (Bank Configuration register 0)
is set to 0xffc5800 (Base address: 0xffc, size = 4 MB, usage: RW and
width = 8 bits) and when do an ioremap64 to map the physical space of
the flash chip into the virtual address, all accesses to the flash chip
are successful. Please note that the virtual address returned by
ioremap64 is different from
0xffc00000.

But, when I do an ioremap first and use the virtual address (the most
significant 12 bits) to program the EBC0_B0CR, all accesses to the
flash chip result in a timeout error on the bus.
The IBM 440GP documentation clearly says that the bits in the EBC0_B0CR
is used to enable the correct chip select signal. Why am I seeing the
above behavior?

I'm actually trying to access a custom chip on the EBI bus using the
same method. I got the same error, so I tried the flash chip....

I'd be thankful if someone could point me to what might be going wrong.
I'd be glad to provide as much information as necessary.

Thanks in advance,
G.Sibi

Chuck Gales · External Since: Jun 03, 2005 Posts: 8

On Sun, 29 Oct 2006 00:48:45 -0700, Sibi wrote:

> Hello all,
>
> I have a question about linux on 440gp and a custom board.
>
> We use the Universal boot-loader, U-boot, to initialize the board and
> then, boot linux. The flash chip on the board is 4 MB in size.
>
> I'm trying to access the flash chip (attached to the External Bus
> Interface) in a custom device driver running in linux. The behavior
> I'm seeing is this: when the EBC0_B0CR (Bank Configuration register 0)
> is set to 0xffc5800 (Base address: 0xffc, size = 4 MB, usage: RW and
> width = 8 bits) and when do an ioremap64 to map the physical space of
> the flash chip into the virtual address, all accesses to the flash chip
> are successful. Please note that the virtual address returned by
> ioremap64 is different from
> 0xffc00000.
>
> But, when I do an ioremap first and use the virtual address (the most
> significant 12 bits) to program the EBC0_B0CR, all accesses to the
> flash chip result in a timeout error on the bus.
> The IBM 440GP documentation clearly says that the bits in the EBC0_B0CR
> is used to enable the correct chip select signal. Why am I seeing the
> above behavior?
>
> I'm actually trying to access a custom chip on the EBI bus using the
> same method. I got the same error, so I tried the flash chip....
>
> I'd be thankful if someone could point me to what might be going wrong.
> I'd be glad to provide as much information as necessary.
>
> Thanks in advance,
> G.Sibi

The EBC Controller needs to be programmed with the Physical Address which
you want to map the Flash chip to. The Virtual Address (which you get
from the ioremap64() is what you use to access the Flash chip from
software. You should never need to reprogram the EBC controller after the
initial configuration by U-Boot.

Chuck

daylitemoon · Joined: Feb 25, 2008 Posts: 1

Hi,

I happened to come across the query regrading EBC peripheral access. Actually I am facing certain problems while writing a device driver in Linux to access a peripheral attached to the EBC. May be you could help me with writing the device driver or cud share ur working driver with me, if possible.

I've assigned a physical address to the EBC peripheral and configured the address in EBC0_B3CR register & have set the access parameters in the EBC0_B3AP register. The whole issue is that I've to work with I/O memory which is non-cacheable. Iam requesting for the memory range 0x80000000 to 0x8000FFFFF using request_mem_region & have got a virtual memory address using the ioremap(). I've been asked to ensure that the TLB entries corresponding to this address range is marked as cache inhibited & guarded so as to make the memory range non cacheable. Do I have to manually set up the TLB entries or this is taken care by the kernel's ioremap() function? BTW, Iam working on the PPC405Exr processor. Any help would be appreciated.

If possible, cud u share ur working driver wid me? Thanks in advance.

Regards,
Daylite Moon